1. Field of the Invention
The present invention relates to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET), and more particularly to a method for fabricating a MOSFET, wherein a source/drain electrode is formed by selectively etching an oxide film to expose a region where source/drain junctions will be formed, and then implanting impurity ions in the exposed region.
2. Description of the Prior Art
FIGS. 1A to 1D illustrate sequential steps of a conventional method for fabricating a P-channel MOSFET, respectively. In accordance with this method, a first-conduction type silicon substrate 1 is first prepared, and then a well is formed in the upper portion of the silicon substrate 1 using second-conduction type impurity ions which are different from the first-conduction type, as shown in FIG. 1A. The first-conduction type impurity ions are then implanted in a portion of the well corresponding to an active region. By these ion implantation steps, the well is provided with an element-isolating region as well as the active region. The well is also formed with a channel region 3. Thereafter, a gate oxide film 4 and a gate electrode 5 are formed on the channel region 3 in a sequential manner. The second-conduction type impurity ions are implanted in accordance with a pocket ion implanting method, thereby forming a pocket region. In this case, the amount of implanted ions is controlled as the concentration of the first-conduction type impurity ions implanted in the channel region is formed in the active region. By this control, the threshold voltage can be controlled. The punch-through characteristic may also be improved by controlling the ion implantation energy in the channel region formed in the active region.
Over the resulting structure shown in FIG. 1A, a first oxide film 6 is then deposited, as shown in FIG. 1B. Thereafter, the first oxide film 6 is etched in accordance with a dry etch method to expose the active region, as shown in FIG. 1C, At this time, oxide film spacers 7 are formed respectively on opposite side walls of the gate electrode 5 which is formed by the ion implantation. Subsequently, the exposed active region is ion-implanted with the first-conduction type impurity ions, thereby forming source/drain junctions 14 and 15.
On the resulting structure, source/drain electrodes 8 are then formed, as shown in FIG. 1D. In order to insulate the source/drain electrodes 8 from the gate electrode 5, a second oxide film 9 is deposited over the entire upper surface of the structure shown in FIG. 1C prior to the formation of the source/drain electrodes 8. The second oxide film 9 is etched using a photo mask in accordance with the dry etch method.
As mentioned above, the above-mentioned MOSFET fabricating method involves the formation of the oxide film 9 which is carried out by first forming the source/drain junctions 14 and 15 and then annealing the resulting structure under the condition that the source/drain junctions 14 and 15 are exposed. In other words, the second oxide film 9 is required for an electrical insulation between the gate electrode 5 and source/drain electrodes 8. Due to the formation of the second oxide film 9, however, the impurity ions doped in the source/drain junctions 14 and 15 are inevitably laterally diffused. As a result, the thermal budget increases while the channel length is reduced. Furthermore, boron, which exhibits a very high diffusion rate as compared to other impurities, is used for the formation of source/drain junctions in the case of P-channel MOSFETs. In this case, the annealing process greatly limits the design of P-channel MOSFETs.
In other words, the thermal budget applied to the junctions increases in the conventional fabrication of P-channel MOSFETs because the oxide film 9 is formed using the annealing process under the condition that the surfaces of the junctions 14 and 15 are exposed.
Moreover, the impurity ions doped in the source/drain junctions 14 and 15 are laterally diffused under the above-mentioned condition, thereby causing the channel to have a reduced length. As a result, it is difficult to achieve a high integration of semiconductor devices. The lateral diffusion of the impurity ions doped in the source/drain junctions 14 and 15 also increases the overlapping area between the junctions and field oxide film 2. This results in a degradation in the insulating characteristic between neighboring active regions. It is also difficult to reduce MOSFETs to a desired size.